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LAN9312 Datasheet(PDF) 190 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 190 Page - SMSC Corporation |
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190 / 458 page ![]() High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.2 (04-08-08) 190 SMSC LAN9312 DATASHEET 3 Flow Control on Multicast Frame (FCMULT) When this bit is set, the Host MAC will assert back pressure when the AFC level is reached and a multicast frame is received. This field has no function in full-duplex mode. 0: Flow Control on Multicast Frame Disabled 1: Flow Control on Multicast Frame Enabled R/W 0b 2 Flow Control on Broadcast Frame (FCBRD) When this bit is set, the Host MAC will assert back pressure when the AFC level is reached and a broadcast frame is received. This field has no function in full-duplex mode. 0: Flow Control on Broadcast Frame Disabled 1: Flow Control on Broadcast Frame Enabled R/W 0b 1 Flow Control on Address Decode (FCADD) When this bit is set, the Host MAC will assert back pressure when the AFC level is reached and a frame addressed to the Host MAC is received. This field has no function in full-duplex mode. 0: Flow Control on Address Decode Disabled 1: Flow Control on Address Decode Enabled R/W 0b 0 Flow Control on Any Frame (FCANY) When this bit is set, the Host MAC will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the Host MAC is operating in full-duplex mode. When this mode is enabled during half-duplex operation, the Flow Controller does not decode the Host MAC address and will send a JAM upon receipt of a valid preamble (i.e., immediately at the beginning of the next frame after the RX Data FIFO level is reached). When this mode is enabled during full-duplex operation, the Flow Controller will immediately instruct the Host MAC to send a pause frame when the RX Data FIFO level is reached. The MAC will queue the pause frame transmission for the next available window. Setting this bit overrides bits [3:1] of this register. R/W 0b Table 14.2 Backpressure Duration Bit Mapping BACKPRESSURE DURATION [7:4] 100Mbs Mode 10Mbs Mode 0h 5uS 7.2uS 1h 10uS 12.2uS 2h 15uS 17.2uS 3h 25uS 27.2uS 4h 50uS 52.2uS 5h 100uS 102.2uS 6h 150uS 152.2uS 7h 200uS 202.2uS BITS DESCRIPTION TYPE DEFAULT |
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