LAN9312 datasheet(244/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

244

SMSC LAN9312

DATASHEET

14.2.7.2

PHY Management Interface Access Register (PMI_ACCESS)

This register is used to control the management cycles to the PHYs. A PHY access is initiated when

this register is written. This register is used in conjunction with the PHY Management Interface Data

Note:

This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to

Section 10.2.4, "EEPROM Loader," on page 149 for additional information.

Offset:

0A8h

EEPROM Loader

Access Only

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

15:11

PHY Address (PHY_ADDR)

These bits select the PHY device being accessed. Refer to Section 7.1.1,

"PHY Addressing," on page 82 for information on PHY address

assignments.

00000b

10:6

MII Register Index (MIIRINDA)

These bits select the desired MII register in the PHY. Refer to Section 14.4,

"Ethernet PHY Control and Status Registers," on page 286 for detailed

descriptions on all PHY registers.

00000b

5:2

RESERVED

Note:

This bit must always be written with a value of 1.

RESERVED

LAN9312 Datasheet(PDF) 244 Page - SMSC Corporation

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