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LAN9312 Datasheet(PDF) 243 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 243 Page - SMSC Corporation |
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243 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 243 Revision 1.2 (04-08-08) DATASHEET 14.2.7 PHY Management Interface (PMI) The PMI registers are used (by the EEPROM Loader only) to indirectly access the PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status Registers," on page 286 for additional information on the PHY registers. Note: These registers are only accessible by the EEPROM Loader and NOT by the Host bus. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for additional information. 14.2.7.1 PHY Management Interface Data Register (PMI_DATA) This register is used in conjunction with the PHY Management Interface Access Register (PMI_ACCESS) to perform write operations to the PHYs. Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for additional information. Offset: 0A4h EEPROM Loader Access Only Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:0 MII Data This field contains the value written to the PHYs. For a write operation, this register should be first written with the desired data. WO 00000000h |
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