LAN9312 datasheet(239/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

239

Revision 1.2 (04-08-08)

DATASHEET

14.2.6.7

Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)

This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This

re gist er is used in conju n ct ion wit h Swit ch Fabric MAC Address High Register

(SWITCH_MAC_ADDRH). The contents of this register are optionally loaded from the EEPROM at

power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant

byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte

(bits [31:24]) is loaded from address 04h of the EEPROM. These EEPROM values are also loaded

into the Host MAC Address Low Register (HMAC_ADDRL). The Host can update the contents of this

field after the initialization process has completed.

Refer to Section 9.6, "Host MAC Address," on page 119 for details on how the EEPROM Loader loads

this register. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for information on using the

EEPROM Loader.

Offset:

1F4h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Physical Address[31:0]

This field contains the lower 32-bits (31:0) of the physical address of the

Switch Fabric MACs.

R/W

FF0F8000h

LAN9312 Datasheet(PDF) 239 Page - SMSC Corporation