LAN9312 datasheet(275/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

275

Revision 1.2 (04-08-08)

DATASHEET

14.3.3

Host MAC Address Low Register (HMAC_ADDRL)

This read/write register contains the lower 32-bits of the physical address of the Host MAC. The

contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM

Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is

loaded from address 01h of the EEPROM. The most significant byte of this register is loaded from

address 04h of the EEPROM. Section 9.6, "Host MAC Address," on page 119 details the byte ordering

of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet

physical address. Please refer to Section 10.2, "I2C/Microwire Master EEPROM Controller," on

page 137 for more information on the EEPROM Loader.

Offset:

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Physical Address [31:0]

This field contains the lower 32-bits (31:0) of the Physical Address of the

Host MAC. The content of this field is undefined until loaded from the

EEPROM at power-on. The host can update the contents of this field after

the initialization process has completed.

R/W

FFFFFFFFh

LAN9312 Datasheet(PDF) 275 Page - SMSC Corporation