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CMV12000

Functional Description

Datasheet

• PUBLIC

DS000603

• v6-00 • 2023-Sep-22

│ 23

The LVDS input clock should only start after the rise time of the supplies. The external reset pin

should be released at least 1

μs after the supplies have become stable. The first frame can be

requested 1

μs after the reset pin has been released. An optional SPI upload (to program the

sequencer) is possible 1

μs after the reset pin has been released. In this case, the FRAME_REQ

pulse must be postponed until after the SPI upload has been completed.

7.2.6

Reset Sequence

If a sensor reset is necessary while the sensor is running, the next sequence should be followed:

Figure 13:

Reset Sequence

The on-board sequencer will be reset and all programming registers will return to their default start-up

values when a falling edge is detected on the SYS_RES_N pin. After the reset there is a minimum

time of 1

μs needed, before a FRAME_REQ pulse can be sent.

When a switch from 12-bit to 10-bit or 8-bit mode (or vice versa) is necessary, the following sequence

should be followed:

Figure 14:

Reset Sequence with Changing Bit Mode

The following SPI register should be uploaded in this mode: Bit_mode (address 118): set to desired bit

resolution mode.

1μs

LVDS_CLK

SYS_RES_N

FRAME_REQ

1μs

LVDS_CLK

SYS_RES_N

FRAME_REQ

Bit mode settings

SPI upload

1μs

CMV12000 Datasheet(PDF) 24 Page - ams-OSRAM AG

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