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RH850 Datasheet(PDF) 60 Page - Renesas Technology Corp

Part # RH850
Description  Renesas Microcontroller
PDF  68 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RH850 Datasheet(HTML) 60 Page - Renesas Technology Corp

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RH850/C1M-A
Section 3 Electrical Characteristics
Page 60 of 68
R01DS0491EJ0100 Rev.1.00
Mar.31.2025
3.5.3
Error Detect Characteristics
Table 3.35
Error Detect Characteristics
Error Detect Item
Set Threshold
(Default Setting)
Detect Time
Resolver signal error monitor output
amplitude voltage*1
Set register
RDC3AnDIAG0.EXCETH[7:0]
0.102 × (RVCC±5%) [Vp-p]
220 [µs] (typ.),
2 [ms] (max.)
Breaking of resolver signal
(Direct current bias supply method)
VSINMNT-VCOM or VCOSMNT-VCOM*2
The register used for setting threshold
when DC resolver is selected
RDC3AnDIAG0.SGBDTH[7:0]
COM + 0.35 × (RVCC±5%)
[VDC]
10 [ms] (max.)
The register used for setting threshold
when VR resolver is selected
RDC3AnDIAG0.SGBTH[7:0]
COM + 0.08 × (RVCC±5%)
[VDC]
R/D conversion error
(over control declination)
Recognition level for internal control
declination (ε)
*3
High side
00CA8H
*4
Low side
7F358H
Resolver signal power short error
Pins S1, S2, S3, and S4
0.9 × (RVCC±5%) [VDC]
0.08 [ms] (max.)
Pins RSO and COM
0.8 × (RVCC±5%) [VDC]
Resolver signal ground short error
Pins S1, S2, S3, and S4
0.1 × (RVCC±5%) [VDC]
0.08 [ms] (max.)
Pins RSO and COM
0.2 × (RVCC±5%) [VDC]
Sum square amplitude error
Integral value of sum square of monitor
output amplitude voltage (sin, cos) with an
interval within the excitation period
High side
0.8 × (RVCC±5%) [Vp-p]
*5
Low side
0.2 × (RVCC±5%) [Vp-p]
Note 1.
Determined as an error, when both of SINMNT and COSMNT become under threshold.
Note 2.
Determined as an error, when DC level changed over threshold.
Note 3.
Determined as over, when control declination becomes over high side threshold, or under low side threshold.
Note 4.
Determined as an error, when control declination recognition rate becomes over 50% as average of period set by the EDPS
[1:0] bits in the RDC3AnDIAG1 register (default is about 7.4 ms). It might not be detected, when the error continuous period is
shorter than detect period.
Note 5.
Dependent on the excitation frequency and amplitude error excitation period count settings.



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