RH850 datasheet(21/68 Pages) RENESAS

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RH850/C1M-A

Section 2 Pins

Page 21 of 68

R01DS0491EJ0100 Rev.1.00

Mar.31.2025

Table 2.1

C1M-A2 Pin Function (3/3)

Pin Name

I/O

Function

SCInSCK (n = 0 to 2)

SCIn clock

SCInTXD (n = 0 to 2)

SCIn transmit data

TAPAnESO (n = 0 to 5)

Hi-Z control

TAPAnUN (n = 0 to 2)

Motor control output U phase (negative)

TAPAnUP (n = 0 to 2)

Motor control output U phase (positive)

TAPAnVN (n = 0 to 2)

Motor control output V phase (negative)

TAPAnVP (n = 0 to 2)

Motor control output V phase (positive)

TAPAnWN (n = 0 to 2)

Motor control output W phase (negative)

TAPAnWP (n = 0 to 2)

Motor control output W phase (positive)

TPBAnO (n = 0, 1)

TPBAn channel output

TAUDnIm (n = 0 to 3, m = 0 to 15)

TAUDn channel input m

TAUDnOm (n = 0 to 3, m = 0 to 15)

TAUDn channel output m

TAUJnIm (n = 0 to 1, m = 0 to 3)

TAUJn channel input m

TAUJnOm (n = 0 to 1, m = 0 to 3)

TAUJn channel output m

TSG3nOm (n = 0 to 2, m = 0 to 7)

TSG3n channel output m

X1, X2

―

Crystal oscillator connections

RSENTnRX (n = 0 to 3)

SENT input

RSENTnSPCO (n = 0 to 3)

SENT control output

RDC3An_OUT_U (n = 0, 1)

RDC U-phase output

RDC3An_OUT_V (n = 0, 1)

RDC V-phase output

RDC3An_OUT_W (n = 0, 1)

RDC W-phase output

CAUTION

In C1M-A2, use SCI30 with the alternative function pins within the same port group.

● When serial clock I/O signals are used

─ P5_0(SCI0RXD), P5_1(SCI0TXD), P5_2(SCI0SCK)

● When serial clock I/O signals are not used

─ P5_0(SCI0RXD), P5_1(SCI0TXD)

─ P7_2(SCI0RXD), P7_4(SCI0TXD)

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