RH850 datasheet(39/72 Pages) RENESAS

39 / 72 page

RH850/P1M-E

Section 3 Electrical Specifications

Page

39 of 72

R01DS0505ED0100 Rev.1.00

September 30, 2025

Note 1.

tRESW1 is the time over which assertion of the reset signal is required to continue until the supply of internal

clock signals becomes stable after all power supplies have been turned on. Release the pin reset after the

periods of tRESW1 and tOSC have elapsed. VCC and EnVCC should be supplied from the same source.

No restriction applies to potential differences between the levels of the VCC/EnVCC supplies, the AnVCC

supply, and the VDD supply during power up.

Note 2.

tRESW2 is the time over which assertion of the reset signal is required until either of the power voltages has

dropped below the lower limit.

Note 3.

The states of I/O pins are not reset during the noise cancellation interval (max. 1.2

μs) of the reset signal

following its assertion while power is being turned off. During that time, do not allow any input of mid-range

potential to a pin or the contention of output data.

Note 4.

If the power is turned off during the programming or erasure of flash memory, the data in the area that was

programmed or erased cannot be guaranteed.

Table 3.4

DPS Products

Conditions: See Section 3.1.1.1, Common Conditions.

Item

Symbol

MIN.

MAX.

Unit

Remarks

Pin reset time at low level for power on

tRESW1

Pin reset time at low level for power off

tRESW2

μs*2

Operating mode setup time

tMDS

1ms

Operating mode hold time

tMDH

1ms

VCC/AnVCC voltage ramp

tVS1

0.02

500

V/ms

VDD voltage ramp

tVS2

500

V/ms

Note:

tOSC: OSC oscillation stabilization time

Figure 3.2

Power UP/Down Timing: DPS Products

RESET

tMDS

tMDH

tRESW2

tRESW1

3.0V

VPOC

VIL

VIH

AnVCC

3.0V

MOSC

tOSC

VDD

1.20V

FLMD0, FLMD1

VCC, EnVCC

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