RX72T datasheet(49/120 Pages) RENESAS

49 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 49 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.2

Recommended operating conditions

Note 1. Comply with the following voltage condition: VCC_USB ≤ VCC ≤ AVCC0 = AVCC1 = AVCC2

Note 2. When the USB interface is not to be used, connect VCC_USB to VCC and VSS_USB to VSS, and set VOLSR.USBVON=0.

Note 3. When not using any of the12-bit A/D converter (unit 0 to 2), 12-bit D/A converter, comparator C, or temperature sensor, connect

AVCC0, AVCC1, and AVCC2 to VCC, and AVSS0, AVSS1, and AVSS2 to VSS, respectively. For details, refer to section

39.6.10, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.

Note 4. When VOLSR.PGAVLS = 0 and ADPGADCR0.PxDEN = 1 (x = 000, 001, 002, 100, 101, 102).

Note 1. Use a multilayer ceramic capacitor with a nominal capacitance of 0.47 µF, for which the sum of the capacitance tolerance and

change in the capacitance under the usage conditions will be no greater than ±30%.

Table 2.2

Recommended operating conditions (1)

Item

Symbol

Min.

Typ.

Max.

Unit

Power supply voltage

VCC*1

2.7

—

5.5

VSS

—

USB power supply voltage*2

When USB in use

VCC_USB*1

3.0

—

3.6

VSS_USB

—

When USB not in

use

VCC_USB

—

VCC

—

VSS_USB

—

VSS

—

Analog power supply voltage*3

AVCC0, AVCC1,

AVCC2*1

3.0

—

5.5

AVSS0, AVSS1,

AVSS2

—0

—

Input voltage

PB1, PB2, PC0, and PD2

Vin

–0.3

—

5.8

P40 to P42, and

P44 to P46

With negative input

enabled*4

–1.0

—

AVCC1 + 0.3

With negative input

disabled

–0.3

—

PH0, PH4

With negative input

enabled*4

–0.5

—

AVCC1 + 0.3

With negative input

disabled

–0.3

—

P43, P47, PH1 to PH3, and PH5 to PH7

–0.3

—

AVCC1 + 0.3

P50 to P55, and P60 to P65

–0.3

—

AVCC2 + 0.3

USB0_DP, USB0_DM

–0.3

—

VCC_USB + 0.3

Other than above

–0.3

—

VCC + 0.3

Operating

temperature

D version

Topr

–40

—

°C

G version

–40

—

105

Table 2.3

Recommended operating conditions (2)

Item

Symbol

Value

Decoupling capacitance for stabilizing the internal voltage

CVCL

0.47 µF ± 30%*1

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