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RX72T Datasheet(PDF) 85 Page - Renesas Technology Corp |
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RX72T Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 120 page ![]() R01DS0331EJ0110 Rev.1.10 Page 85 of 120 Oct 06, 2023 RX72T Group 2. Electrical Characteristics 2.4.6.7 A/D Converter Trigger Note 1. tPBcyc: PCLKB cycle Figure 2.44 A/D Converter Trigger Input Timing 2.4.6.8 CAC Note 1. tPBcyc: PCLKB cycle Note 2. tcac: CAC count clock source cycle Table 2.34 A/D Converter Trigger Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Max. Unit*1 Test Conditions A/D converter A/D converter trigger input pulse width tTRGW 1.5 — tPBcyc Figure 2.44 Table 2.35 CAC Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item*1, *2 Symbol Min.*1, *2 Max. Unit Test Conditions CAC CACREF input pulse width tPBcyc ≤ tcac tCACREF 4.5 tcac + 3 tPBcyc —ns tPBcyc > tcac 5 tcac + 6.5 tPBcyc — ADTRG0#, ADTRG1#, ADTRG2# PCLKB tTRGW |
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