ADSP-21990 datasheet(30/50 Pages) AD

30 / 50 page

Rev. A

Page 30 of 50

August 2007

ADSP-21990

External Port Read Cycle Timing

Table 10 and Figure 11 describe external port read operations.

For additional information on the ACK signal, see the discus-

sion on Page 28.

Table 10. External Port Read Cycle Timing

Parameter

1, 2

Min

Max

Unit

Timing Requirements

tAKW

ACK Strobe Pulse Width

tHCLK

tRDA

RD Asserted to Data Access Setup

tEMICLK – 5 + W

tADA

Address Valid to Data Access Setup

tEMICLK + W

tSDA

Chip Select Asserted to Data Access Setup

tEMICLK + W

tSD

Data Valid to RD Deasserted Setup

tHRD

RD Deasserted to Data Invalid Hold

tDRSAK

ACK Delay from XMS Low

0.5tEMICLK – 1

Switching Characteristics

tCSRS

Chip Select Asserted to RD Asserted Delay

0.5tEMICLK – 3

tARS

Address Valid to RD Setup and Delay

0.5tEMICLK – 3

tRSCS

RD Deasserted to Chip Select Deasserted Setup

0.5tEMICLK – 2

tRW

RD Strobe Pulse Width

tEMICLK–2 + W

tRSA

RD Deasserted to Address Invalid Setup

0.5tHCLK – 2

tRWR

RD Deasserted to WR, RD Asserted

tHCLK

1 tEMICLK is the external memory interface clock period. tHCLK is the peripheral clock period.

2 These are timing parameters that are based on worst-case operating conditions.

3 W = (number of wait states specified in wait register)

tEMICLK.

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