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830S21AMILF Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # 830S21AMILF
Description  1-to-1 2.5V, 3.3V Differential-to-LVCMOS/LVTTL
PDF  10 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

830S21AMILF Datasheet(HTML) 4 Page - Renesas Technology Corp

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© 2015-2024 Renesas Electronics Corporation
November 7, 2024
830S21I Datasheet
Table 3D. Differential DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
NOTE 1:VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
IIH
Input High Current
VDD = VIN = 3.465V or 2.625V
150
µA
IIL
Input Low Current
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.5
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5
VDD – 0.85
V
VBB
Output Voltage Reference
VDD – 1.4
VDD – 1.3
VDD – 1.2
V
Parameter Symbol
Test Conditions
Minimum Typical Maximum
Unit
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay, NOTE 1
0.95
1.95
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
525
ps
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz – 20MHz)
0.11
1
ps
tR / tF
Output Rise/Fall Time
20% to 80%
85
500
ps
odc
Output Duty Cycle
ƒ  266MHz
47
53
%
Parameter Symbol
Test Conditions
Minimum Typical Maximum
Unit
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay, NOTE 1
1
2
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
550
ps
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz – 20MHz)
0.11
1
ps
tR / tF
Output Rise/Fall Time
20% to 80%
125
500
ps
odc
Output Duty Cycle
ƒ  266MHz
47
53
%



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