7

© 2015-2024 Renesas Electronics Corporation

November 7, 2024

830S21I Datasheet

Parameter Measurement Information, continued

Part-to-Part Skew

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and

R2/R1 = 0.609.

Figure 1. Single-Ended Signal Driving Differential Input

Qx

Qy

tsk(pp)

V

DD

2

V

DD

2

Par t 1

Par t 2

V_REF

Single Ended Clock Input

VDD

CLK

nCLK

R1

1K

C1

0.1u

R2

1K