AD5602 datasheet(20/23 Pages) AD

Part #	AD5602

Description	2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs with I2C Compatible Interface in LFCSP and SC70

PDF	23 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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20 / 23 page

AD5602/AD5612/AD5622

Data Sheet

Rev. E | Page 20 of 23

HIGH SPEED MODE

High speed mode communication commences after the master

addresses all devices connected to the bus with the Master

Code 00001XXX to indicate that a high speed mode transfer is

to begin. No device connected to the bus is permitted to

acknowledge the high speed master code, therefore, the code is

followed by a no acknowledge.

The master must then issue a repeated start followed by the

device address. The selected device then acknowledges the

address. All devices continue to operate in high speed mode

until the master issues a stop condition. When the stop

condition is issued, the devices return to standard/fast mode.

START BY

MASTER

ACK. BY

AD56x2

NACK.

SERIAL BUS ADDRESS BYTE

HS-MODE MASTER CODE

HIGH-SPEED MODE

FAST MODE

SCL

SDA

R/W

Figure 49. Placing the AD5602/AD5612/AD5622 into High Speed Mode

AD5602 Datasheet(PDF) 20 Page - Analog Devices