Data Sheet

AD5602/AD5612/AD5622

Rev. E | Page 3 of 23

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

A, B, W, Y Versions1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

DAC output unloaded

Resolution

Bits

AD5602

8

AD5612

10

AD5622

12

Relative Accuracy2

AD5602

±0.5

LSB

B, Y versions

AD5612

±0.5

LSB

B, Y versions

±4

LSB

A version

AD5622

±2

LSB

B, Y versions

±6

LSB

A, W versions

Differential Nonlinearity2

±1

LSB

Guaranteed monotonic by design

Zero Code Error

0.5

10

mV

All 0s loaded to DAC register

Offset Error

±0.063

±10

mV

Full-Scale Error

0.5

mV

All 1s loaded to DAC register

Gain Error

±0.0004

±0.037

% of FSR

Zero Code Error Drift

5

µV/°C

Gain Temperature Coefficient

2

ppm of FSR/°C

OUTPUT CHARACTERISTICS3

Output Voltage Range

0

VDD

V

Output Voltage Settling Time

6

10

µs

Code ¼ to ¾

Slew Rate

0.5

V/µs

Capacitive Load Stability

470

pF

RL = ∞

1000

pF

RL = 2 kΩ

Output Noise Spectral Density

120

nV/Hz

DAC code = midscale, 10 kHz

Noise

2

DAC code = midscale, 0.1 Hz to 10 Hz

bandwidth

Digital-to-Analog Glitch Impulse

5

nV-sec

1 LSB change around major carry

Digital Feedthrough

0.2

nV-sec

DC Output Impedance

0.5

Ω

Short Circuit Current

15

mA

VDD = 3 V/5 V

LOGIC INPUTS (SDA, SCL)

IIN, Input Current

±1

µA

VINL, Input Low Voltage

0.3 × VDD

V

VINH, Input High Voltage

0.7 × VDD

V

CIN, Pin Capacitance

2

pF

VHYST, Input Hysteresis

0.1 × VDD

V

LOGIC OUTPUTS (OPEN DRAIN)

VOL, Output Low Voltage

0.4

V

ISINK = 3 mA

0.6

V

ISINK = 6 mA

Floating State Leakage Current

±1

µA

Floating State Output Capacitance

2

pF