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AD5683R Datasheet(PDF) 8 Page - Analog Devices

Part # AD5683R
Description  TDS Measurement System for Water Quality Monitoring
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5683R Datasheet(HTML) 8 Page - Analog Devices

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CN-0411
Circuit Note
Rev. 0 | Page 8 of 12
Auto-Ranging Conductivity Measurement
For a given type of solution and conductivity probe used, the
range of conductivity measurement range encompasses multiple
gain resistance settings. Furthermore, to prevent the excitation
voltage from exceeding the rated voltage of the conductivity
cell, the excitation voltage value must change along with the
gain resistance. The software is capable of automatically setting
the gain resistance and the excitation voltage to the range of the
conductivity of the solution. This ensures that the conductivity
reading is always being measured at the most reliable setting.
The method of auto-ranging the conductivity measurement is
described in Figure 12.
Figure 12. Auto-Ranging Conductivity Measurement Flowchart
Calibration Procedure
The system is capable of two calibration methods, a zero-scale
calibration and through a reference precision resistance. The
calibration method used to obtain the measurements discussed
in Figure 15 uses a reference precision resistance, which can
either be a 20 Ω or 200 Ω resistor as shown in Figure 5. It is in
these resistance ranges that the on-resistance of the multiplexer
has a significant effect on the conductivity measurement. The
output of this calibration is an offset resistance value, which is
added to the gain resistance used in the computation of
conductivity. Figure 13 shows the procedure to perform this
calibration.
Figure 13. Flowchart of Calibration Procedure through a Reference
Resistance
The zero-scale calibration performs the zero-scale calibration of
the AD7124-8, which eliminates the output bias voltages of the
sample-and-hold topology. This ensures that a zero-input to the
conductivity cell corresponds to the ADCs zero code. Place a
shunt in Pin 2 and Pin 3 of Jumper Header P6 of the CN-0411
board. The AD7124-8 is commanded to perform system zero-
scale calibration on both the positive and negative voltages of
the conductivity signal. This stores the zero-input voltage level
in the ADCs offset registers and is automatically considered in
every sample reading.
Both these two calibration methods need to be done only once
for each board since the software stores the output of the
calibration procedures.
System Accuracy
From Equation 9, the computation of conductivity depends on
the two output voltages of the sample-and-hold topology, RGAIN,
and the DAC output voltage. RGAIN resistors below the MΩ
range have 0.1% tolerance while the 2 MΩ and 20 MΩ resistors
have 1% tolerance. Added to the resistances in the simple
voltage divider network shown in Figure 3 are the on-
resistances of the multiplexer ADG1608 and the conductivity
cell switch ADG884, which are maximum at 17.4 Ω and 0.96 Ω,
respectively. The input bias currents and input offset current
from the instrumentation amplifier introduces a voltage, which
scales with the gain resistance and the resistance of the solution.
The B-grade AD8220 has a max input bias current of 10 pA for
each input and a max input offset current of 0.6 pA, which
makes a total input bias current of 20.6 pA. At 20 MΩ, this
constitutes a 20.6 pA × 20 MΩ = 412 µV input bias voltage.
Moreover, at a gain of 10, the AD8220 has a 0.2% max gain
error. Computing conductivity directly from a known precision
resistance measures the system accuracy and accounts for all
these factors, including the ones introduced by the sample-and-
hold topology, such as the drop voltage in Equation 4.
START
SET MULTIPLEXER
TO HIGHEST
GAIN RESISTANCE
(20MΩ)
READ ADC INPUT
V+ AND V–
YES
NO
PERFORM CONDUCTIVITY
MEASUREMENT AND
TEMPERATURE
MEASUREMENT
CALCULATE TDS
DROP GAIN
RESISTANCE
BY 1 DECADE
V+ + V– > 0.3 × 2VEXC
SET DAC TO
OUTPUT VEXC = 400mV
(OR SPECIFIED USER
DAC VOLTAGE VDAC)
SET VEXC =
VDEF × VEXC
V+ + V–
START
SHORT TERMINALS
3 AND 4, OR 5 AND 6,
IN JUMPER P5
PERFORM ADC SAMPLING
AND COMPUTE V+ AND V–
FROM THE INPUT
POSITIVE AND NEGATIVE VOLTAGES
COMPUTE OFFSET RESISTANCE
ROFFSET =
WHERE:
RREF IS THE REFERENCE PRECISION RESISTOR TOLERANCE
VEXC IS THE CURRENT EXCITATION VOLTAGE VALUE
V+ IS THE POSITIVE SAMPLE-AND-HOLD OUTPUT VOLTAGE
V– IS THE NEGATIVE SAMPLE-AND-HOLD OUTPUT VOLTAGE
– RGAIN
RFEF (2(VEXC) – 2(V+ + V–))
2(V+ + V–))
END



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