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Copyright © 2013 Future Technology Devices International Limited

VDrive3 Datasheet

Version 1.2

Document Reference No.: FT_000699

Clearance No.: FTDI#

335

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VDrive3 Electrical Details

6.1

SPI Interface Timing

The following timing diagrams are for the VNC1L Legacy Interface mode of SPI slave.

SCLK

SS#

MOSI

MISO

Figure 6.1 – VDrive2 SPI example

To start the data transfer process SS# needs to be set to high, and remain high for the entire read cycle.

Once the read cycle is complete SS# needs to be set to low for at least one clock cycle to allow another

data transfer cycle to occur.

The first bit of MOSI is the R/W bit, receiving a logic high for this bit allows data to be read from the

VDrive3. The second bit is the address bit, ADD; this bit is used to select data read from the data register

when set to logic high, and read from the status register when set to logic low. During an SPI Read cycle,

a package of data is transmitted from the VDRIVE3 on the MISO line from the time of the first clock cycle

after the SPI ADD bit, with the MSB transmitted first.

After the data has been transferred the status of MISO can be checked to determine if the data read is

new data as indicated by a transmitted logic low. If old data is transmitted, as indicated by a transmitted

logic high, the read cycle needs to be repeated to get new data.

SCLK

SS#

MOSI

MISO

Figure 6.2 – VDrive3 SPI example

To start the data transfer process SS# needs to be set to high for the entire write cycle. Once the write

cycle is complete SS# needs to be set low for at least one clock cycle to allow another data transfer cycle

to occur.