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Copyright © 2013 Future Technology Devices International Limited

VDrive3 Datasheet

Version 1.2

Document Reference No.: FT_000699

Clearance No.: FTDI#

335

The first bit of MOSI is the R/W bit, receiving a logic low for this bit allows data to be written to the

VDrive3. The second bit is the address bit, ADD, this bit is used to select a data write to the data register

when set to logic high, and to the status register when set to logic low. During an SPI Write cycle a

package of data is transmitted to the VDRIVE3 on the MOSI line from the time of the first clock cycle

after the SPI ADD bit, with the MSB transmitted first.

After the data has been transferred, the status of MISO can be checked to determine if the data written

has been accepted. If a logic low is given for the status bit, it can be determined that the data write was

successful. If a logic high is given for the status bit, the internal buffer of the device receiving data is full,

and the same write cycle should be repeated.

SCLK

MOSI

MISO

Figure 6.3 – VDrive3 SPI example

Time

Description

Min

Typical

Max

Unit

T1

SCLK Period

83

-

-

ns

T2

SCLK High

20

-

-

ns

T3

SCLK Low

20

-

-

ns

T4

Input Setup Time

10

-

-

ns

T5

Input Setup Time

10

-

-

ns

T6

Input Hold Time

2

-

-

ns

T7

Output Valid Time

-

-

20

ns

Table 6-1 – SPI Interface Pin-Out