ST18952 datasheet(13/67 Pages) STMICROELECTRONICS

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ST18952

Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and

peripherals registers are mapped in these address spaces.

Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own

control interface.

Table 4.1

Data/instruction bus and corresponding address bus.

Depending on the calculation mode, the D950Core DCU computes operands which can be

considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able

to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit,

including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic

and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included.

The tables below illustrate the different types of word length and word format available for

manipulation.

Table 4.2

Summary of possible word lengths and formats

Data/instruction bus

Corresponding address bus

Bidirectional

16-bit

Unidirectional

16-bit

Bidirectional

16-bit

Unidirectional

16-bit

Bidirectional

16-bit

Unidirectional

16-bit

1-bit word

8-bit word

16-bit word signed / unsigned

32-bit word signed / unsigned

40-bit word signed / unsigned

Format

Minimum

Maximum

fractional

signed

- 1

+ 0.999969481

unsigned

+ 0.99996948

integer

signed

- 32768

+ 32767

unsigned

+ 65535

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