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ST18952 Datasheet(PDF) 35 Page - STMicroelectronics |
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ST18952 Datasheet(HTML) 35 Page - STMicroelectronics |
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35 / 67 page ![]() 35/66 ST18952 10 SIO The ST18952 has two synchronous serial input/output (SIO) ports which link to serial devices such as codecs and to other processors. The SIO ports work in DMA mode. SIO0 uses channels 0 and 1 of the DMA controller, SIO1 uses channels 2 and 3. The chip must be configured for SIO using the DMAR system register (”DMAR: DMA management register” on page 44). For SIO port 0, bits 1 and 0 of the DMAR register must be reset to inhibit external DMA requests (1 and 0) and to allow SIO port 0 communication with the outside. For SIO port 1, bits 3 and 2 of the DMAR register must be reset to inhibit external DMA requests (3 and 2) and to allow SIO port 1 communication with the outside. The SIO ports have the following features: • double-buffered full-duplex operation • frequency up to D950 input clock (33 Mbps for 66 MHz D950) • programmable functions • word length: 8/16 bits (msb first) • up to 8 words per frame • frequency prescaler (by 1 or 3) and divider (by 21 to 28) • synchronization signal: bit length/word length, delayed/not delayed, active level • clock signal: internal/external, active edge • 4 status flags / 2 enabled interrupt requests • data transfers between SIO and memories using DMA |
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