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ST18952 Datasheet(PDF) 52 Page - STMicroelectronics |
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ST18952 Datasheet(HTML) 52 Page - STMicroelectronics |
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52 / 67 page ![]() 52/66 ST18952 Table 15.5 Bus control timing data Control I/O electrical characteristics Figure 15.4 Control I/O timing diagram Table 15.6 Control I/O timing diagram No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t11 DTACK high setup t0/4 t12 DTACK low setup t0/4 t13 DTACK high hold 0 No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t14 CONTROL_IN setup 6.0 t15 CONTROL_OUT high/low delay 3.0 CLKOUT MCLK t15 t0 CONTROL_IN CONTROL_OUT t14 |
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