TPS2359RHHT datasheet(21/51 Pages) TI

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TPS2359

www.ti.com ................................................................................................................................................... SLUS792D – FEBRUARY 2008 – REVISED JUNE 2008

Table 5. Register 2: Channel 3A Configuration (Read/write)

BIT

NAME

DEFAULT

DESCRIPTION

3AFT0

Setting bit increases 3A fault time by 0.5 ms.

3AFT1

Setting bit increases 3A fault time by 1 ms.

3AFT2

Setting bit increases 3A fault time by 2 ms.

3AFT3

Setting bit increases 3A fault time by 4 ms.

3AFT4

Setting bit increases 3A fault time by 8 ms.

3AEN

Clearing bit disables 3A.

3AUV

Setting bit prevents enabling unless OUT3A < bleed down threshold.

3ADS

Clearing bit disconnects OUT3A bleed down resistor.

3AFT[4:0] These five bits adjust the 3A channel fault time. The least-significant bit has a nominal weight of 0.5

ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In

general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be

used. See Setting Fault Time section.

3AEN This bit serves as a master enable for channel 3A. Setting this bit allows the 3A channel to operate

normally, provided the EN3A pin is also asserted. Clearing this bit disables the channel by removing gate drive to

the internal pass FET, regardless of the state of the EN3A pin.

3AUV Setting this bit prevents channel 3A from turning on until OUT3A falls below the bleed down threshold of

100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly

zero before the channel can enable them.

3ADS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT3A to ground.

Systems using redundant power supplies should clear 3ADS to prevent the bleed down resistor from

continuously sinking current.

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