100

10

200

300

75

75

75

75

80

80

80

80

70

70

70

65

65

65

80

80

85

85

55

55

55

60

60

60

400

f

-InputFrequency-MHz

IN

SFDR-dBc

500

600

700

900

800

1000

170

200

400

250

300

350

450

500

550

50

45

55

60

80

75

70

65

85

90

M0049-09

APPLICATION INFORMATION

Theory of Operation

Input Configuration

ADS5463

TYPICAL CHARACTERISTICS (continued)

SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY

Figure 29.

The ADS5463 is a 12-bit, 500-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and

3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion

process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is

captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in

offset binary format.

The analog input for the ADS5463 consists of an analog pseudo-differential buffer followed by a bipolar transistor

track-and-hold (see Figure 30). The analog buffer isolates the source driving the input of the ADC from any

internal switching and presents a high impedance that is easy to drive at high input frequencies, compared to an

ADC without a buffered input. The input common mode is set internally through a 500-

Ω resistor connected from

2.4 V to each of the inputs. This results in a differential input impedance of 1 k

Ω.

16

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