Thisisanexampleblockdiagram.

Low-JitterClockDistribution

ADC

ADS5463

VCO

REF

CDC

(ClockDistributionChip)

CDCM7005

1000MHz(totransmitDAC)

.

.

.

250MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(highorlowjitter)

10MHz

500MHz

Low-JitterOscillator

1000MHz

BPF

LVCMOS

LVPECL

or

LVCMOS

XFMR

AMP

CLKIN

CLKIN

AMP and/orBPFareOptional

125MHz(toDSP)

Thisisanexampleblockdiagram.

Low-JitterClockDistribution

ADC

ADS5463

VCO

REF

CDC

(ClockDistributionChip)

CDCM7005

1000MHz(totransmitDAC)

125MHz(toDSP)

250MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(highorlowjitter)

10MHz

500MHz

Low-JitterOscillator

1000MHz

LVPECL

LVPECL

or

LVCMOS

CLKIN

CLKIN

.

.

.

ADS5463

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 46. Optimum Jitter Clock Circuit

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 47. Acceptable Jitter Clock Circuit

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