71

72

73

74

75

76

77

78

79

80

0

1

2

3

4

5

G022

62.5

63.0

63.5

64.0

64.5

65.0

65.5

66.0

0

1

2

3

4

5

G023

CLK

ADS5463

CLK

0.1

F

m

Clock

Source

S0194-02

ADS5463

Figure 40. SFDR versus Differential Clock Level

Figure 41. SNR versus Differential Clock Level

Figure 40 and Figure 41. For jitter-sensitive applications, the use of a differential clock has some advantages at

the system level. The differential clock allows for common-mode noise rejection at the printed circuit board (PCB)

level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency

applications because the board level clock jitter is superior.

Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At

high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small

amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the

uncertainty in the sampling point associated with a slow slew rate. Figure 42 demonstrates a recommended

method for converting a single-ended clock source into a differential clock; it is similar to the configuration found

on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data

Converters (SLYT075) for more details.

Figure 42. Differential Clock

The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-k

Ω resistors (see

Figure 38). It is recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good

tolerance to clock common-mode variation, as shown in Figure 43 and Figure 44. The internal ADC core uses

both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided,

though even 40/60 is good enough for many applications. Performance degradation as a result of duty cycle can

be seen in Figure 45.

22

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