TMS320DM335 datasheet(41/156 Pages) TI

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TMS320DM335

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS528 – JULY 2008

Table 2-23. DM335 Pin Descriptions (continued)

Name

BGA

Type Group

Power

Reset

Description(4)

Mux Control

(1)

Supply(2)

PD(3)

State

FIELD / GIO070

I/O

VENC

VDD_VOUT

Video Encoder: Field identifier for interlaced

PINMUX1[19:18].FI

/ R2 / PWM3C

/ GIO /

display formats

ELD

VENC

PWM3

GIO: GIO[070]

Digital Video Out: R2

PWM3C(4)

EXTCLK /

I/O

VENC

VDD_VOUT

Video Encoder: External clock input, used if

PINMUX1[21:20].EX

GIO069 / B2 /

/ GIO /

clock rates > 27 MHz are needed, e.g. 74.25 TCLK

PWM3D

VENC

MHz for HDTV digital output

PWM3

GIO: GIO[069]

Digital Video Out: B2

PWM3D(4)

VCLK / GIO068

I/O

VENC

VDD_VOUT

out L

Video Encoder: Video Output Clock

PINMUX1[22].VCLK

/ GIO

GIO: GIO[068](4)

VREF

A I/O Video

Video DAC: Reference voltage output

DAC

(0.45V, 0.1uF to GND)

IOUT

A I/O Video

Video DAC: Pre video buffer DAC output

DAC

(1000 ohm to VFB)

IBIAS

A I/O Video

Video DAC: External resistor (2550 Ohms to

DAC

GND) connection for current bias

configuration

VFB

A I/O Video

Video DAC: Pre video buffer DAC output

DAC

(1000 ohm to IOUT, 1070 ohm to TVOUT)

TVOUT

A I/O Video

VDDA18_DAC

Video DAC: Analog Composite NTSC/PAL

DAC

output (SeeFigure 5-31 andFigure 5-32 for

circuit connection)

VDDA18V_DAC

PWR Video

Video DAC: Analog 1.8V power

DAC

VSSA_DAC

GND Video

Video DAC: Analog 1.8V ground

DAC

DDR_CLK

I/O

DDR

VDD_DDR

out L

DDR Data Clock

DDR_CLK

I/O

DDR

VDD_DDR

out H

DDR Complementary Data Clock

DDR_RAS

I/O

DDR

VDD_DDR

out H

DDR Row Address Strobe

DDR_CAS

I/O

DDR

VDD_DDR

out H

DDR Column Address Strobe

DDR_WE

W10

I/O

DDR

VDD_DDR

out H

DDR Write Enable (active low)

DDR_CS

I/O

DDR

VDD_DDR

out H

DDR Chip Select (active low)

DDR_CKE

V10

I/O

DDR

VDD_DDR

out L

DDR Clock Enable

DDR_DQM[1]

U15

I/O

DDR

VDD_DDR

out L

Data mask outputs: DDR_DQM1: For

DDR_DQ[15:8]

DDR_DQM[0]

T12

I/O

DDR

VDD_DDR

out L

Data mask outputs: DDR_DQM0: For

DDR_DQ[7:0]

DDR_DQS[1]

V15

I/O

DDR

VDD_DDR

Data strobe input/outputs for each byte of

the 16 bit data bus used to synchronize the

data transfers. Output to DDR when writing

and inputs when reading.

DDR_DQS1: For DDR_DQ[15:8]

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