TMS320DM335 datasheet(76/156 Pages) TI

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3.6.2

PLLC1

TMS320DM335

Digital Media System-on-Chip (DMSoC)

SPRS528 – JULY 2008

www.ti.com

PLLC1 provides most of the DM335 clocks. Software controls PLLC1 operation through the PLLC1

registers. The following list, Table 3-14, and Figure 3-3 describe the customizations of PLLC1 in the

DM335.

• Provides primary DM335 system clock

• Software configurable

• Accepts clock input or internal oscillator input

• PLL pre-divider value is fixed to (/8)

• PLL multiplier value is programmable

• PLL post-divider

• Only SYSCLK[4:1] are used

• SYSCLK1 divider value is fixed to (/2)

• SYSCLK2 divider value is fixed to (/4)

• SYSCLK3 divider value is programmable

• SYSCLK4 divider value is programmable to (/4) or (/2)

• SYSCLKBP divider value is fixed to (/3)

• SYSCLK1 is routed to the ARM Subsystem

• SYSCLK2 is routed to peripherals

• SYSCLK3 is routed to the VPBE module

• SYSCLK4 is routed to the VPSS module

• AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1

• SYSCLKBP is routed to the output pin CLKOUT2

Table 3-14. PLLC1 Output Clocks

Output Clock

Used By

PLLDIV

Notes

Divider

SYSCLK1

ARM Subsystem

Fixed divider

SYSCLK2

Peripherals

Fixed divider

SYSCLK3

VPBE (VENC module)

Programmable divider (used to get 27

MHz for VENC)

SYSCLK4

VPSS

/4 or /2

Programmable divider

AUXCLK

Peripherals, CLKOUT1

none

No divider

SYSCLKBP

CLKOUT2

Fixed divider

Detailed Device Description

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