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TMS320DM335 Datasheet(PDF) 135 Page - Texas Instruments |
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TMS320DM335 Datasheet(HTML) 135 Page - Texas Instruments |
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135 / 156 page ![]() SPI_CLK (ClockPolarity=0) SPI_CLK (ClockPolarity=1) SPI_DI (Input) SPI_DO (Output) 13 MSBIN DATA LSBIN LSBOUT MSBOUT DATA 17 15 14 16 SPI_EN 19 18 TMS320DM335 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS528 – JULY 2008 SPI Master Mode Timings (Clock Phase = 1) Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38) DM335 NO. UNIT MIN MAX Setup time, SPI_DI (input) valid before SPI_CLK (output) 13 tsu(DIV-CLKL) Clock Polarity = 0 .5P + 3 ns rising edge Setup time, SPI_DI (in put) valid before SPI_CLK (output) 14 tsu(DIV-CLKH) Clock Polarity = 1 .5P + 3 ns falling edge Hold time, SPI_DI (input) valid after SPI_CLK (output) rising 15 th(CLKL-DIV) Clock Polarity = 0 .5P + 3 ns edge Hold time, SPI_DI (input) valid after SPI_CLK (output) falling 16 th(CLKH-DIV) Clock Polarity = 1 .5P + 3 ns edge Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase = 1] (see Figure 5-38) DM335 NO. PARAMETER UNIT MIN MAX Delay time, SPI_CLK (output) falling edge to SPI_DO 17 td(CLKL-DOV) Clock Polarity = 0 -4 5 ns (output) transition Delay time, SPI_CLK (output) rising edge to SPI_DO 18 td(CLKH-DOV) Clock Polarity = 1 -4 5 ns (output) transition Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling 2P+.5C 19 td(ENL-CLKH/L) (1) ns edge (1) 20 td(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance P(2) (2) ns (1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1). (2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1). Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1) Submit Documentation Feedback DM335 Peripheral Information and Electrical Specifications 135 |
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