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OMAP3530 Datasheet(PDF) 1 Page - Texas Instruments |
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OMAP3530 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 264 page  1 OMAP3530/25 Applications Processor 1.1 Features OMAP3530/25 Applications Processor www.ti.com SPRS507B – FEBRUARY 2008 – REVISED JULY 2008 • Protected Mode Operation • OMAP3530/25 Applications Processor: • Exceptions Support for Error Detection – OMAP™ 3 Architecture and Program Redirection – MPU Subsystem • Hardware Support for Modulo Loop • 600-MHz ARM Cortex™-A8 Core Operation • NEON™ SIMD Coprocessor • C64x+ L1/L2 Memory Architecture – High Performance Image, Video, Audio – 32K-Byte L1P Program RAM/Cache (Direct (IVA2.2™) Accelerator Subsystem Mapped) • 430-MHz TMS320C64x+™ DSP Core – 80K-Byte L1D Data RAM/Cache (2-Way • Enhanced Direct Memory Access Set-Associative) (EDMA) Controller (128 Independent – 64K-Byte L2 Unified Mapped RAM/Cache Channels) (4-Way Set-Associative) • Video Hardware Accelerators – 32K-Byte L2 Shared SRAM and 16K-Byte L2 – 2D/3D Graphics Accelerator (OMAP3530 ROM Device Only) • C64x+ Instruction Set Features • Tile Based Architecture Delivering up to – Byte-Addressable (8-/16-/32-/64-Bit Data) 10 MPoly/sec – 8-Bit Overflow Protection • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating – Bit-Field Extract, Set, Clear Pixel and Vertex Shader Functionality – Normalization, Saturation. Bit-Counting • Industry Standard API Support: – Compact 16-Bit Instructions OpenGLES 1.1 and 2.0, OpenVG1.0 and – Additional Instructions to Support Complex Direct3D Mobile Multiplies • Fine Grained Task Switching, Load • ARM Cortex™-A8 Core Balancing, and Power Management – ARMv7 Architecture • Programmable High Quality Image • Trust Zone® Anti-Aliasing • Thumb®-2 – Fully Software-Compatible With C64x and • MMU Enhancements ARM9™ – In-Order, Dual-Issue, Superscalar – Commercial and Extended Temperature Microprocessor Core Grades – NEON™ Multimedia Architecture • Advanced Very-Long-Instruction-Word (VLIW) – Over 2x Performance of ARMv6 SIMD TMS320C64x+™ DSP Core – Supports Both Integer and Floating Point – Eight Highly Independent Functional Units SIMD • +Six ALUs (32-/40-Bit), Each Supports – Jazelle® RCT Execution Environment Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Architecture Arithmetic per Clock Cycle – Dynamic Branch Prediction with Branch • Two Multipliers Support Four 16 x 16-Bit Target Address Cache, Global History Multiplies (32-Bit Results) per Clock Buffer, and 8-Entry Return Stack Cycle or Eight 8 x 8-Bit Multiplies (16-Bit – Embedded Trace Macrocell (ETM) Support Results) per Clock Cycle for Non-Invasive Debug – Load-Store Architecture With Non-Aligned Support • ARM Cortex™-A8 Memory Architecture: – 64 32-Bit General-Purpose Registers – 16K-Byte Instruction Cache (4-Way Set-Associative) – Instruction Packing Reduces Code Size – 16K-Byte Data Cache (4-Way – All Instructions Conditional Set-Associative) – Additional C64x+™ Enhancements Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. is a trademark of ~ Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the Copyright © 2008–2008, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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