MAC7101 datasheet(9/710 Pages) FREESCALE

9 / 710 page

Functional Overview

MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Freescale Semiconductor

— Boot from program Flash

— JTAG lockout recovery available

•

Secured Expanded Mode

— All debug features available.

— Boot from off-chip device using the external bus interface

— Program and data Flash memory not available

•

Data Flash Boot Mode

— All debug features available

— Boot from data Flash

•

Secured Data Flash Boot Mode

— No debug features available

— No external bus interface

— Boot from data Flash

— JTAG lockout recovery available

3.2

Low-Power Modes

There are three low-power modes available:

•

Stop Mode (provides the lowest power consumption)

This is a mode in which all MCU clocks are stopped for maximum power savings. Typically, when

stop mode is requested, each module puts itself in a known state and then sends a stop acknowledge

signal to inform the clock module that it can stop the clocks.

•

Pseudo-Stop Mode

The oscillator continues to run and most of the system and peripheral clocks are stopped. If the

respective enable bits are set, the SWT and RTI will continue to run, otherwise they also stop.

•

Doze Mode

This is a mode in which the CPU bus is kept alive and a global doze mode request is sent to all

peripherals asking them to enter low power mode. Typically, when doze mode is requested, each

peripheral can be enabled to enter low power mode or continue normal operation.

Functional Overview

The following is a brief summary of the functional blocks in the MAC7100 devices. For more details refer

to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM).

4.1

32-bit ARM7TDMI-S RISC Core

The MAC7100 family is implemented with an ARM7 CPU. This is a 32-bit RISC core with a three-stage

pipeline for high instruction throughput. The core used across the family is the ARM7TDMI-S, which

supports both 32-bit and 16-bit (THUMB) instruction sets for optimum code density. No architectural

modifications have been made to this core during implementation, enabling the MAC7100 family to

remain compliant to the ARM ISA V4T and existing tool chains. The core is implemented to support big

endian memory systems.

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