MAC7101 datasheet(12/710 Pages) FREESCALE

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MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Functional Overview

Freescale Semiconductor

4.8

CAN 2.0 Software Compatible (FlexCAN) Modules

There are up to four FlexCAN modules on MAC7100 devices; refer to Table 1 for the number of FlexCAN

channels implemented on a specific device. The CAN protocol is primarily, but not only, designed to be

used as a vehicle serial data bus, meeting the specific requirements of this application: real-time processing,

reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. The

FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which

supports both standard and extended message frames. A flexible number of message buffers (up to 32 MBs)

is also supported, which are stored in an embedded RAM dedicated to the FlexCAN module (up to 544

bytes capability).

On MAC7100 devices, the clock source for the FlexCAN can be selected to be derived either from the PLL

clock or the oscillator clock. The FlexCAN also implements a low pass filter which can be used to wake

up the device when activity is detected on the bus, while also enabling rejection of bus noise to help

eliminate instances of false wake. MAC7100 devices implement 32 mailboxes on each CAN module.

4.9

Enhanced Modular I/O Subsystem (eMIOS)

The Enhanced Modular I/O Subsystem (eMIOS) provides functionality to generate or measure time-based

events. The eMIOS module implemented on MAC7100 family devices has 16 unified timer channels

(UCs), each with a 16-bit counter. Each UC is identical and can be configured to provide a wide range of

timer functions. The module implements 3 counter busses for inter-channel synchronization and sharing

common time bases.

Each of the UCs has a single input/output signal associated with it, resulting in a module with 16 external

signals available for the user. The eMIOS module can be independently disabled. Disabling the module

turns off the clock to the module, although some of the module registers remain available to be accessed

by the core via the peripheral bus.

4.10 Serial Peripheral Interfaces (DSPI)

MAC7100 devices implement up to two (Deserial) Serial Peripheral Interface modules (DSPI). Only the

SPI configuration is implemented in the MAC7100 family of devices. Refer to Table 1 for the number of

DSPI channels implemented on a specific device. Each DSPI supports up to eight peripheral chip select

lines, offering selection of up to 8 external devices without external hardware, expandable to 256 with an

external demultiplexer. One of the chip select signals can be used to provide a strobe for the other chip

selects in order to eliminate decoding glitches generated when the chip selects change. This allows

glitch-free selection of up to 128 external devices via external hardware.

The DSPI is implemented with separate transmit and receive FIFOs with a depth of up to four entries.

These FIFOs can be accessed either by the CPU or the eDMA to enable queued operations to be performed.

Each DSPI has a separate DMA request channel for the transmit and the receive sides of the module. For

queued operations the SPI queues reside in system RAM external to the DSPI. Data transfers between the

queues and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host

software. Each queue entry contains both configuration information and data, enabling fast baud rate and

chip select switching between frames with no CPU overhead and no SPI channel dead time.

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