MAC7101 datasheet(13/710 Pages) FREESCALE

13 / 710 page

Functional Overview

MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Freescale Semiconductor

4.11 Enhanced Serial Communications Interfaces (eSCI)

There are up to four Enhanced Serial Communications Interfaces (eSCI) implemented on MAC7100

devices. Refer to Table 1 for the number of eSCI channels implemented on a specific device. The eSCI

provides full duplex, asynchronous, NRZ serial communication with remote devices, including other

MPUs. The eSCI transmitter and receiver operate independently, although they use the same baud rate

generator. The CPU monitors the status of the eSCI, writes the data to be transmitted, and processes

received data. The enhancement offered by this module over other Freescale SCIs is the inclusion of

additional features which support a Local Interconnect Network (LIN) bus master, and complies with the

LIN 2.0 specification. LIN master mode enables handling message frames rather than individual data

packets, thus significantly reducing interrupt overhead (for example, from 13 individual interrupts to one).

4.12 Inter-Integrated Circuit (I2C) Bus Module

The Inter-Integrated Circuit Bus (I2C or IIC) is a two-wire bidirectional serial bus that provides a simple

and efficient method of data exchange between devices. It minimizes the number of external connections

between devices and does not require an external address decoder. The I2C bus is suitable for applications

requiring occasional communications over a short distance between a number of devices. It also provides

flexibility, allowing additional devices to be connected to the bus for further expansion and system

development. The interface is designed to operate at up to 100 Kbps with maximum bus loading and

timing. MAC7100 family devices are capable of operating at higher baud rates, up to a maximum of the

module clock divided by 20, with reduced bus loading. The maximum communication length and the

number of devices that can be connected are limited by the maximum bus capacitance of 400 pF.

4.13 Periodic Interrupt Timer (PIT) Module

The PIT is an array of timers that can be used to generate interrupts and trigger eDMA channels. It also

provides a dedicated Real-Time Interrupt (RTI) timer, which runs on a separate clock and can be used for

system wake-up from low-power modes.

The PIT provides eleven programmable timers offering a range of functions. All of the timers are 24-bit

wide down-counters. Once zero is reached, a trigger can be generated, then the counter is reloaded with

the start value and continues to be decremented. The value of the decrementer can be read at any time. The

eleven timers provide one Real Time Interrupt (RTI), four general purpose timers, four eDMA trigger

timers, and two timers used to trigger ATD conversions.

4.14 Miscellaneous Control Module (MCM) and Cross-Bar

Switch (XBS)

The Miscellaneous Control Module (MCM) provides several control functions for the MAC7100 family

Standard Product Platform (SPP), including program-visible information regarding configuration and

revision levels, a reset status register, a software watchdog timer, wake-up control for exiting sleep modes,

the control registers for the crossbar switch, and generic access error information for the processor core.

MAC7101 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc