MAC7101 datasheet(14/710 Pages) FREESCALE

14 / 710 page

MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Functional Overview

Freescale Semiconductor

The software watchdog timer (SWT) is contained within the MCM and supports either interrupt or reset

generation on the occurrence of a time-out event. The SWT also supports a windowed time period,

requiring the writing of the watchdog key within a specified time window. The source for the SWT clock

is controlled by the clock and reset generator module (CRG).

The MCM also configures the crossbar switch (XBS) address map to steer access to the crossbar slave

ports in order to provide remapping operations. Following reset, the mapping is determined by the chip

mode entered. Following reset the Flash, external bus, and RAM can be remapped as necessary.

4.15 System Services Module (SSM)

The SSM contains information on device configuration and the status of the eDMA controller.

4.16 Voltage Regulator Module (VREG)

The voltage regulator (VREG) module provides the internal voltage for the on-chip logic, which enables

devices in the MAC7100 family to be supplied with a single 5V power supply source. The VREG module

is a dual output voltage regulator providing two 2.5 V (typical) supplies that differ in the amount of current

that can be sourced by each. The regulator input voltage range is from 3.3 V up to 5 V. In low-power modes

of operation the voltage regulator output can be reduced in order to further assist with power saving. The

VREG can also be shut down by connecting the VDDR pin to VSSR.

4.17 System Clocks (OSC and CRG)

The Pierce oscillator (OSC) coupled with the Clock and Reset Generator (CRG) provide the internal clock

signals for the core and all peripheral modules. The system clock can be supplied to the MCU in several

ways, enabling support for a range of system operating frequencies:

•

From the oscillator, with a frequency set by an external, 16 MHz maximum, crystal reference

•

From the on-chip phase-locked loop, using the oscillator clock as a reference

•

From the PLL in self-clocking mode

The clock generated by the oscillator or the phase-locked loop (PLL) provides the main system clock

frequency, fSYS. The system clock is used throughout the device to drive the core and the memories. The

IPS peripherals use a clock equal to fSYS ÷ 2.

The program Flash memory is supplied by both fSYS and fSYS ÷ 2. fSYS is used for access to the Flash

controller, but the interleaved Flash arrays operate at half the system frequency to allow enough time to

access the array, enabling the memory controller to achieve close to single-cycle access times.

The CAN modules may be configured to utilize either the peripheral clock (fSYS ÷ 2) or the oscillator clock

(OSCCLK). This allows the user to select the CAN clock based on the required jitter performance.

The Periodic Interrupt Timer (PIT) and Software Watchdog Timer (SWT) can be configured to run from

the oscillator or the PLL generated clock. This allows these functions to continue to run during low-power

operating modes if required.

MAC7101 Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc