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STE10/100

5.3 Transceiver(XCVR) Registers

There are 11 16-bit registers supporting the transceiver portion of STE10/100, including 7 basic registers de-

fined according to clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28 “Physi-

cal Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of the IEEE802.3u standard.

In addition, 4 special registers are provided for advanced chip control and status.

Note: 1. Since only Double Word access is supported for Register R/W in the STE10/100, the higher word(bit 31~16) of the XCVR registers

(XR0~XR10) should be ignored.

Table 7. Transceiver registers list

Offset from

base address

of CSR

Reg. Index

Name

b4h

XR0

XCR

XCVR Control Register

b8h

XR1

XSR

XCVR Status Register

bch

XR2

PID1

PHY Identifier 1

c0h

XR3

PID2

PHY Identifier 2

c4h

XR4

ANA

Auto-Negotiation Advertisement Register

c8h

XR5

ANLPA

Auto-Negotiation Link Partner Ability Register

cch

XR6

ANE

Auto-Negotiation Expansion Register

d0h

XR7

XMC

XCVR Mode Control Register

d4h

XR8

XCIIS

XCVR Configuration Information and Interrupt Status Register

d8h

XR9

XIE

XCVR Interrupt Enable Register

dch

XR10

100CTR

100BASE-TX PHY Control/Status Register

Table 8. Transceiver registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

XR0(offset = b4h) - XCR, XCVR Control Register. The default value is chosen as listed below.

XRST

Transceiver Reset control.

1: reset transceiver. This bit will be cleared by STE10/100 after

transceiver reset has completed.

R/W

XLBEN

Transceiver loop-back mode select.

1: transceiver loop-back mode is selected. OM (CSR6 bits

11,10) of must contain 00.

R/W

SPSEL

Network Speed select. This bit will be ignored if Auto-

Negotiation is enabled (ANEN, XR0 bit 12).

1:100Mbps is selected.

0:10Mbps is selected.

R/W

ANEN

Auto-Negotiation ability control.

1: Auto-Negotiation function is enabled.

0: Auto-Negotiation is disabled.

R/W

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