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STE10 Datasheet(PDF) 56 Page - STMicroelectronics

Part # STE10
Description  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
PDF  66 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE10 Datasheet(HTML) 56 Page - STMicroelectronics

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STE10/100
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7.0 GENERAL EEPROM FORMAT DESCRIPTION
Table 14. Connection Type Definition
Offset
Length
Description
0
2
STE10/100 Signature: 0x81, 0x09
2
1
Format major version: 0x02,
old ROM format version 0x01 is for STE10/100-MAC only.
3
1
Format minor version: 0x00
4
4
Reserved
86
IEEE network address: ID
1, ID2, ID3, ID4, ID5, ID6
E
1
IEEE ID checksum1:
Sm
0=0, carry=0
SUM=Sm
6 where Smi=(Smi-1<<1)+(carry from shift)+IDi
F
1
IEEE ID checksum2:
Reserved, should be zero.
10
1
PHY type, 0xFF: Internal PHY (STE10/100 only)
11
1
Reserved, should be zero.
12
2
Default Connection Type, see Table 15
14
0B
Reserved, should be zero.
1F
1
Flow Control Field,
00: Disable Flow Control function,
01: Enable Flow Control function
20
2
PCI Device ID.
22
2
PCI Vendor ID.
24
2
PCI Subsystem ID.
26
2
PCI Subsystem Vendor ID.
28
1
MIN_GNT value.
29
1
MAX_LAT value.
2A
4
Cardbus CIS pointer.
2E
2
CSR18 (CR) bit 31-16 recall data.
30
4E
Reserved, should be zero.
7E
2
CheckSum, the least significant two bytes of FCS for data stored in offset 0..7D of
EEPROM



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