STE10 datasheet(40/66 Pages) STMICROELECTRONICS

Part #	STE10

Description	PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

PDF	66 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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40 / 66 page

STE10/100

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13-12

-----

Reserved

Loss of carrier

No carrier

Late collision

Excessive collision

Heartbeat fail

6-3

Collision count

-----

Reserved

Under-run error

Deferred

TDES1

Interrupt completed

Last descriptor

First descriptor

28,27

---

Reserved

Disable add CRC function

TER

End of Ring

TCH

2nd address chain. Indicates that the buffer 2 address is the next descriptor address

DPD

Disable padding function

---

Reserved

21-11

TBS2

Buffer 2 size

10-0

TBS1

Buffer 1 size

TDES2

31~0

BA1

Buffer Address 1. No alignment limitations imposed on the transmission buffer address.

TDES3

31~0

BA2

Buffer Address 2. No alignment limitations imposed on the transmission buffer address.

Table 12. Transmit Descriptor Descriptions

Bit#

Name

Descriptions

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