Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Interrupt Controller
Page 24 of 132
© Philips Electronics N.V. 2005
C1
C2
C3
C4
C5
Machine
Cycle
E
Interrupt
Goes
Active
Interrupt
Latched
Interrupts
Are Poled
Long Call to
Interrupt
Vector Address
Interrupt Routine
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP
.
[Figure 7]
Interrupt Response Timing Diagram
The polling cycle/LCALL sequence is illustrated in [Figure 7]. Note that if an interrupt of higher priority
level goes active prior to the instruction labeled C3 in [Figure 7], then in accordance with the above
rules it will be vectored to during C5 and C6, without any instruction of the lower priority routine having
been executed.
Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to
the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and
in other cases it doesn’t. It never clears the Serial Port flag. This has to be done in the user’s software.
It clears an external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-
generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save
the PSW) and reloads the PC with an address that depends on the source of the interrupt being vec-
tored to, as shown in column “vector address” in [Table 2].
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction
informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes
from the stack and reloads the Program Counter. Execution of the interrupted program continues from
where it left off. Note that a simple RET instruction would also have returned execution to the inter-
rupted program, but it would have left the interrupt control system thinking an interrupt was still in pro-
gress, making future interrupts impossible.
5.1.3.3.
External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or
clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at
the t01_intx_n_i pin. If ITx = 1, external interrupt x is edge triggered. In this mode if the interrupt
input (t01_int0_n_i for IT0, t01_int1_n_i for IT1) shows a high to low transition, interrupt request
flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are not
sampled, there is no minimum low duration specified. IEx will be automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external source has to hold the request active until the
requested interrupt is actually generated. Then it has to deactivate the request before the interrupt
service routine is completed, or else another interrupt will be generated.
5.1.3.4.
Response Time
The t01_int0_n_i and t01_int1_n_i levels are inverted and latched into IE0 and IE1. The values
are not actually polled by the circuitry until the next start of an instruction. If a request is active and
conditions are right for it to be acknowledged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of
three complete machine cycles elapse between activation of an external interrupt request and the
beginning of execution of the first instruction of the service routine.
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