Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 58 of 132
© Philips Electronics N.V. 2005
These figures contain the following abbreviations:
Abbreviation Explanation
S
Start condition
SLA
7-bit slave address
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level at SDA)
Data
8-bit data byte
P
Stop condition
In [Figure 21] to [Figure 24], circles are used to indicate when the serial interrupt flag is set. The num-
bers in the circles show the status code held in the S1STA register. At these points, a service routine
must be executed to continue or complete the serial transfer. These service routines are not critical
since the serial transfer is suspended until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in S1STA is used to branch to the appropri-
ate service routine. For each status code, the required software action and details of the following
serial transfer are given in [Table 10] to [Table 14].
Master Transmitter mode (not available for slave-only version)
In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see
[Figure 21]). Before the Master Transmitter mode can be entered, S1CON must be initialized as follows:
7
6
5
4
3
2
1
0
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
bit rate
1
0
0
0
X
bit rate
CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to logic 1 to enable SIO1. If the AA bit is
reset, SIO1 will not acknowledge its own slave address or the general call address in the event of
another device becoming master of the bus. In other words, if AA is reset, SIO0 cannot enter a Slave
mode. STA, STO, and SI must be reset.
The Master Transmitter mode may now be entered by setting the STA bit using the SETB instruction.
The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes
free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in
the status register (S1STA) will be 08H. This status code must be used to vector to an interrupt service
routine that loads S1DAT with the slave address and the data direction bit (SLA+W). The SI bit in S1CON
must then be reset before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgment bit has
been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are
possible. There are 18H, 20H, or 38H for the Master mode and also 68H, 78H, or B0H if the Slave
mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is
detailed in [Table 10]. After a repeated start condition (state 10H). SIO1 may switch to the Master Re-
ceiver mode by loading S1DAT with SLA+R).
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