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LFXP Datasheet(PDF) 63 Page - Lattice Semiconductor |
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LFXP Datasheet(HTML) 63 Page - Lattice Semiconductor |
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63 / 130 page ![]() 4-4 Pinout Information Lattice Semiconductor LatticeXP Family Data Sheet Pin Information Summary 1 XP3 XP6 Pin Type 100 TQFP 144 TQFP 208 PQFP 144 TQFP 208 PQFP 256 fpBGA Single Ended User I/O 62 100 136 100 142 188 Differential Pair User I/O 2 19 35 56 35 58 80 Configuration Dedicated 11 11 11 11 11 11 Muxed 14 14 14 14 14 14 TAP 555555 Dedicated (total without supplies) 666666 VCC 248488 VCCAUX 222224 VCCPLL 222222 VCCIO Bank0 112122 Bank1 112122 Bank2 112122 Bank3 112122 Bank4 122222 Bank5 112122 Bank6 112122 Bank7 112122 GND 10 13 24 13 24 24 GNDPLL 222222 NC 006000 Single Ended/Differential I/O per Bank 2 Bank0 8/2 12/3 20/8 12/3 20/8 26/11 Bank1 9/0 12/2 18/6 12/2 18/6 26/11 Bank2 8/3 12/5 14/6 12/5 17/7 21/9 Bank3 6/2 13/5 14/6 13/5 14/6 21/9 Bank4 5/2 14/6 21/9 14/6 21/9 26/11 Bank5 12/4 12/4 21/9 12/4 21/9 26/11 Bank6 4/2 13/5 14/6 13/5 17/7 21/9 Bank7 10/4 12/5 14/6 12/5 14/6 21/9 VCCJ 111111 1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for more information. |
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