LFXP datasheet(28/130 Pages) LATTICE

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2-25

Architecture

Lattice Semiconductor

LatticeXP Family Data Sheet

Table 2-8. Supported Output Standards

Hot Socketing

The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power-

down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os

remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage

into I/O pins is controlled to within speciﬁed limits, which allows easy integration with the rest of the system.

These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications.

Sleep Mode

The LatticeXP “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up

to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the

SLEEPN pin.

During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os

are tri-stated. Do not enter Sleep Mode during device programming or conﬁguration operation. In Sleep Mode,

power supplies can be maintained in their normal operating range, eliminating the need for external switching of

power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes.

Output Standard

Drive

VCCIO (Nom.)

Single-ended Interfaces

LVTTL

4mA, 8mA, 12mA, 16mA, 20mA

3.3

LVCMOS33

4mA, 8mA, 12mA 16mA, 20mA

3.3

LVCMOS25

4mA, 8mA, 12mA 16mA, 20mA

2.5

LVCMOS18

4mA, 8mA, 12mA 16mA

1.8

LVCMOS15

4mA, 8mA

1.5

LVCMOS12

2mA, 6mA

1.2

LVCMOS33, Open Drain

4mA, 8mA, 12mA 16mA, 20mA

—

LVCMOS25, Open Drain

4mA, 8mA, 12mA 16mA, 20mA

—

LVCMOS18, Open Drain

4mA, 8mA, 12mA 16mA

—

LVCMOS15, Open Drain

4mA, 8mA

—

LVCMOS12, Open Drain

2mA. 6mA

—

PCI33

N/A

3.3

HSTL18 Class I, II, III

N/A

1.8

HSTL15 Class I, III

N/A

1.5

SSTL3 Class I, II

N/A

3.3

SSTL2 Class I, II

N/A

2.5

SSTL18 Class I

N/A

1.8

Differential Interfaces

Differential SSTL3, Class I, II

N/A

3.3

Differential SSTL2, Class I, II

N/A

2.5

Differential SSTL18, Class I

N/A

1.8

Differential HSTL18, Class I, II, III

N/A

1.8

Differential HSTL15, Class I, III

N/A

1.5

LVDS

N/A

2.5

BLVDS

N/A

2.5

LVPECL

N/A

3.3

1. Emulated with external resistors.

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