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LFXP Datasheet(PDF) 64 Page - Lattice Semiconductor

Part # LFXP
Description  LatticeXP Family Data Sheet
PDF  130 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFXP Datasheet(HTML) 64 Page - Lattice Semiconductor

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Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Pin Information Summary
1 (Cont.)
XP10
XP15
XP20
Pin Type
256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA
Single Ended User I/O
188
244
188
268
300
188
268
340
Differential Pair User I/O
2
76
104
76
112
128
76
112
144
Configuration
Dedicated
11
11
11
11
11
11
11
11
Muxed
14
14
14
14
14
14
14
14
TAP
55555555
Dedicated
(total without supplies)
66666666
VCC
814814
28814
28
VCCAUX
4444
12
44
12
VCCPLL
22222222
VCCIO
Bank0
25254254
Bank1
25254254
Bank2
24244244
Bank3
24244244
Bank4
25254254
Bank5
25254254
Bank6
24244244
Bank7
24244244
GND
24
50
24
50
56
24
50
56
GNDPLL
22222222
NC
0240
0400
0
0
Single Ended/
Differential I/O
per Bank
2
Bank0
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank1
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank2
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank3
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank4
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank5
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank6
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank7
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
VCCJ
11111111
1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for
more information.



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