LFXP datasheet(15/130 Pages) LATTICE

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2-12

Architecture

Lattice Semiconductor

LatticeXP Family Data Sheet

Table 2-6. sysMEM Block Conﬁgurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual and Pseudo-Dual Port Modes

Figure 2-14 shows the four basic memory conﬁgurations and their input/output names. In all the sysMEM RAM

modes the input data and address for the ports are registered at the input of the memory array. The output data of

the memory is optionally registered at the output.

Memory Mode

Conﬁgurations

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

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