33291L datasheet(14/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

SERIAL OUTPUT (SO)

The serial output (SO) pin is the tri-stateable output from

the Shift register. The SO pin remains in a high impedance

state until the CS pin goes to a logic low state. The SO data

reports the drain status, either high or low relative to the

previous command word. The SO pin changes state on the

rising edge of SCLK and reads out on the falling edge of

SCLK. When an output is OFF and not faulted, the

corresponding SO data-bit is a high state. When an output is

ON, and there is no fault, the corresponding data-bit on the

SO pin will be a low logic state. The SI/SO shifting of data

follows a first-in-first-out (FIFO) protocol with both input and

output words transferring the MSB first. Referring to

Figure 17, the DO bit is the MSB corresponding to Output 7

relative to the previous command word. The SO pin is not

affected by the status of the RST pin.

RESET (RST)

The 33291L Reset (RST) pin is active low. It is used to

clear the SPI Shift register. In doing so, all output switches

are set at OFF. With the device in a system with an MCU,

upon initial system power-up, the MCU holds the RST pin of

the device in a logic low state, ensuring all outputs to be OFF

until both the VDD and VPWR pin voltages are adequate for

predictable operation. After the 33291L is reset, the MCU is

ready to assert system control with all output switches initially

OFF.

If the VPWR pin of the 33291L experiences a low voltage,

following normal operation, the MCU should pull the RST pin

low to shut down the outputs and clear the input data register.

The RST pin is active low and has an internal pull-down

incorporated to ensure operational predictability should the

external pull-down of the MCU open circuit. The internal pull-

down is only 25

μA, affording safe and easy interfacing to the

MCU. The RST pin of the 33291L should be pulled to a logic

low state for a duration of at least 250 ns to ensure reliable a

reset.

A simple power ON reset delay of the system can be

programmed through the use of an RC network comprised of

a shunt capacitor from the RST pin to Ground and a resistor

to VDD, illustrated in Figure 16. Care should be exercised

ensuring proper discharge of the capacitor. Careful attention

eliminates adverse delay of the RST and damage of the MCU

if it pulls the Reset line low, thereby accomplishing

initialization for turn ON delay. It may be easier to incorporate

delay into the software program and use a parallel port pin of

the MCU to control the 33291L RST pin.

Figure 16. Power ON Reset

SHORT FAULT PROTECT DISABLE (SFPD)

The Short Fault Protect Disable (SFPD) pin is used to

prevent the outputs from latching-off due to an overcurrent

condition. This feature provides control of incandescent lamp

loads where in-rush currents exceed the device’s analog

current limits. Essentially the SFPD pin determines whether

the 33291L output(s) will instantly shut down upon sensing an

output short or remain ON in a current limiting mode of

operation until the output short is removed or thermal

shutdown is reached. If the SFPD pin is tied to VDD = 5.0 V

the 33291L output(s) will remain ON in a current limited mode

of operation upon encountering a load short to supply or

overcurrent condition. When the SFPD pin is grounded, a

short circuit will immediately shut down only the output

affected. Other outputs not having a fault condition will

operate normally. The short circuit operation is addressed in

more detail later.

VDD

RDLY

CDLY

Reset

μA

Reset

MCU

33291

33291L Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc

33291L Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc

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