33291L datasheet(20/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

FUNCTIONAL DESCRIPTION

The eight output-off open-load faults are therefore most

easily detected.

If for a specific output the initial SI command bit were a

logic low, when calling for the output to be programmed on,

the next word command entered into the corresponding bit

returns with a logic high on SO. An output overcurrent fault

would be indicated. An overcurrent fault is always reported by

the SO output and is independent of the logic state existing

on the SFPD pin. When the SFPD pin is in a logic high state,

an overcurrent condition will be reported on the SO pin.

However, limiting output current is in effect and the output is

permitted to operate if the overcurrent condition does not

drive output into an overtemperature fault. An

overtemperature fault will shut down the specific output

effected for the duration of the overtemperature condition.

Overcurrent and overtemperature faults are often related.

Turning the effected output switches OFF and waiting for

some time to allow the output to cool down should make

these types of faults go away. Soft overcurrent faults can

sometimes be determined over hard short faults and

overtemperature faults by observing the time required for the

device to recover. However, in general overcurrent and

overtemperature faults cannot be differentiated in normal

application usage.

An advantage of the synchronous serial output is multiple

faults can be detected with only one (SO) pin being used for

fault status reporting.

If VPWR experiences an overvoltage condition, all outputs

will immediately be turned OFF and remain latched OFF. A

new command word is required to turn the outputs back ON

following an overvoltage condition.

Output Voltage Clamping

Each output of the 33291L incorporates an internal voltage

clamp to provide fast turn-off and transient protection of the

output. Each clamp independently limits the drain-to-source

voltage to 53 V at drain currents of 0.5 A and keeps the

output transistors from avalanching by causing the transient

energy to be dissipated in the linear mode (see Figure 20).

The total energy clamped (EJ) can be calculated by

multiplying the current area under the current curve (IA) times

the clamp voltage (VCL) times the duration the clamp is active

(t).

Characterization of the output clamps, using a single pulse

non-repetitive method at 0.5 A, indicates the maximum

energy to be 50 mJ at 150

°C junction temperature per output.

Figure 20. Output Voltage Clamping

THERMAL CHARACTERIZATION

THERMAL MODEL

Logic functions take up a very small area of the die and

generate negligible power. In contrast, the output transistors

take up most of the die area and are the primary contributors

of power generation. The thermal model illustrated in

Figure 21, page 21, was developed for the 33291L mounted

on a typical PC board. The model is accurate for both steady

state and transient thermal conditions. The components Rd0

through Rd7 represent the steady state thermal resistance of

the silicon die for transistor outputs 0 through 7, while Cd0

through Cd7 represent the corresponding thermal

capacitance of the silicone die translator outputs and plastic.

The device area and die thickness determine the values of

these specific components.

The thermal impedance of the package from the internal

mounting flag to the outside environment is represented by

the terms Rpkg and Cpkg. The steady state thermal resistance

of leads and the PC board make up the steady state package

thermal resistance, Rpkg. The thermal capacitance of the

package is made up of the combined capacitance of the flag

and the PC board. The mode compound was not modeled as

a specific component but it is factored into the other overall

component values.

The battery voltage in the thermal model represents the

ambient temperature the device and PC board are subjected

to. The IPWR current source represents the total power

dissipation and is calculated by totalling the power dissipation

of each individual output transistor. This is easily

accomplished by knowing RDS(ON) and load current of the

individual outputs.

Very satisfactory steady state and transient results are

experienced with this thermal model. Tests indicate the

model accuracy to have less than 10 percent error. Output

interaction with an adjacent output is believed to be the main

contributor to the thermal inaccuracy. Tests indicate little or

no detectable thermal effects caused by distant output

transistors isolated by one or more other outputs. Tests were

Current

Area (IA)

VPWR

Time

GND

Drain-to-Source ON

Voltage (VDS(ON))

Drain Current

(ID = 0.5 A)

Drain-to-Source Clamp

Voltage (VCL = 65 V)

Drain Voltage

Clamp Energy

(EJ = IA x VCL x t)

33291L Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc

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