M30245 datasheet(49/266 Pages) RENESAS

49 / 266 page

M30245 Group

Frequency Synthesizer Circuit

Rev.2.00

Oct 16, 2006

page 49 of 264

REJ03B0005-0200

Multiplier

Clock fVCO is a multiplied up version of clock fPIN (See Figure 1.27). The relationship between fVCO and

the clock (fPIN) input to the multiplier from the prescaler is as follows:

• fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM.

• Setting FSM to 255 disables the multiplier and fVCO = fPIN.

Note 1: n must be chosen such that fVCO equals 48 MHz.

Note 2: Minimum fPIN is 1 MHz. Maximum fPIN is 12 MHz.

Figure 1.27. Frequency Synthesizer Multiply register (FSM)

Divider

Clock fSYN is a divided down version of clock fVCO (See Figure 1.28). The relationship between fSYN and the

clock (fVCO) input to the divider from the multiplier is as follows:

• fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD.

NOTE: fSYN = fVCO / (m+1) when the divide by 3 option (bit 4 at address 03DB16) is set and when m = 2.

• Setting FSD to 255 disables the divider and fSYN = fVCO.

fPIN

FSM

fVCO

Dec(n)

Hex(n)

1 MHz

48.00 MHz

2 MHz

48.00 MHz

4 MHz

48.00 MHz

6 MHz

48.00 MHz

8 MHz

48.00 MHz

12 MHz

48.00 MHz

MSB

LSB

Bit 6

Bit 1

Bit 0

Bit 2

Bit 5

Bit 4

Bit 3

Bit 7

Address: 03DD16

Access:

R/W

Reset:

FF16

fPIN x 2(n+1)

f VCO =

fVCO /2(m+1)

fSYN

fVCO

FSD

fSYN

Dec(m)

Hex(m)

48.00 MHz

8.00 MHz

48.00 MHz

16.00 MHz (Note)

MSB

LSB

Bit 6

Bit 1

Bit 0

Address: 03DF16

Access: R/W

Reset:

FF16

Bit 2

Bit 7

Bit 5

Bit 4

Bit 3

Note:

if FSCCR4 = 1 and m = 2

fVCO / (m+1)

fSYN =

127

187.50 KHz

48.00 M z

12.00 MHz

48.00 M z

6.00 MHz

Figure 1.28. Frequency Synthesizer Divide register (FSD)

M30245 Datasheet(PDF) 49 Page - Renesas Technology Corp

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