| Electronic Components Datasheet Search |
|
M34286 Datasheet(PDF) 5 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M34286 Datasheet(HTML) 5 Page - Renesas Technology Corp |
|
5 / 66 page ![]() Rev.1.00 Aug 06, 2008 page 5 of 64 REJ03B0251-0100 4286 Group CONNECTIONS OF UNUSED PINS (Note when connecting to VSS and VDD) • Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise. PORT FUNCTION Control bits 1 bit Output: 2 bits Input: 3 bits 4 bits 1 bit Control instructions SD RD CLD SZD OEA IAE IAE OGA IAG SCAR RCAR Control registers PU1, PU2 PU0 PU0 Output structure P-channel open-drain P-channel open-drain P-channel open-drain CMOS Input/ Output I/O (8) I/O (2) Input (1) I/O (4) Output (1) Remark Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Pin D0–D7 E0 E1 E2 G0–G3 CARR Port Port D Port E Port G Port CARR DEFINITION OF CLOCK AND CYCLE • System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the Oscillation dividing instruction. CCK, CCK2, or CCK4 instruction can be executed only once. After one of their instruction is executed once, the operation is same as the NOP instruction though the same or another frequency dividing instruction is executed. The system clock returns to its initial state (f(XIN)/8) when system is returnd from RAM back-up mode. Pin D0–D7 E0, E1 E2 G0–G3 CARR Connection Open (Set the output latch to “1” ). Open (Set the output latch to “0” ). Connect to VDD. Open (Set the output latch to “1” ). Open (Set the output latch to “0” ). Connect to VDD. Open. Connect to VSS. Open (Set the output latch to “1” ). Open (Set the output latch to “0” ). Connect to VDD. Open. Usage condition Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. System clock f(XIN)/8 f(XIN) f(XIN)/2 f(XIN)/4 Instruction clock f(XIN)/32 f(XIN)/4 f(XIN)/8 f(XIN)/16 Oscillation dividing instruction No use CCK used CCK2 used CCK4 used • Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle. • Machine cycle The machine cycle is the cycle required to execute the instruction. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |