| Electronic Components Datasheet Search |
|
M66592FP Datasheet(PDF) 49 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M66592FP Datasheet(HTML) 49 Page - Renesas Technology Corp |
|
49 / 127 page ![]() M66592F P/W G Rev 1.00 2004.10.01 page 49 of 125 3.1.4 USB data bus resistor control Figure 3.1 shows a diagram of the connections between the controller and the USB connectors. The controller has a built-in pull-up resistor for the D+ signal. “1” should be set for the DPRPU bit of the SYSCFG register, then the D+ line is pulled up. The pull-up power supply is AFE33V. Also, the controller has a built-in terminal resistor for use when the D+ and D- signals are operating at Hi-Speed, and a built-in output resistor for Full-Speed operation. The controller automatically switches the built-in resistor after connection with the PC, by means of reset handshake, suspended state and resume detection. If a disconnection from the PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0). If “0” is set for the DPRPU bit of the SYSCFG register, the pull-up resistor (or the terminal resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection. M66592FP/WG VBUS USB connector 1 3 2 4 GND D- D+ Vbus DM DP RERFIN 5.6K Ω Impedance control has to be taken into consideration when designing the D+ and D- lines. 1~10µF The capacitance of 1 to 10 µF stipulated by the USB specification is necessary for the VBUS signal. Figure 3.1 UBS connector connections 3.1.5 Clock supply control Figure 3.2 shows a block diagram of the controller clock control. Frequency of the input clock for the XIN pin should be selected using the XTAL bit of the SYSCFG register, while the oscillation buffer is enabled using the XCKE bit and the clock supply is controlled using the RCKE, PLLC, and SCKE bits. For information on the register control timing, please refer to 3.1.7, State transition timing. Auto clock supply Low-power control Input clock Oscillation buffer XCKE (bit13) PLLC, SCKE (bit11, bit10) Internal clock PLL Clock control unit RCKE (bit12) Divider circuit PCUT (bit1) ATCKM (bit8) Figure 3.2 Clock control block |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |