M66592FP datasheet(67/127 Pages) RENESAS

67 / 127 page

M66592F P/W G

Rev 1.00 2004.10.01 page 67 of 125

3.2.4

BEMP interrupt

The table below shows the conditions under which BEMP interrupts are generated. The cause of a BEMP for the

various pipes should be confirmed using the pertinent bit of the BEMPSTS register. If an interrupt has been disabled

using the BEMPE bit of the INTENB0 register, the interrupt request is set in the pertinent bit of the BEMPSTS

controller clears the BEMP bit of the INTSTS0 register. If a pipe is under the conditions such as (1)(a), (1)(b), or (2)

bellow, the controller sets “1” to a pertinent bit of the BEMPSTS register. In this case, the controller generats BEMP

interrupt, if software enables PIPENBEMPE bit of the BEMPENB register and BEMPE bit of the INTENB0 register.

When software clears all enabled bits of the BEMPSTS register, the controller clears the BEMP bit.

(1) When the sending direction (writing to the buffer memory) has been set

When all of the data stored in the buffer memory has been sent

If a double buffer is being used for the buffer memory, however, the following conditions are observed.

(a) A BEMP interrupt is generated if the buffer on one side is empty and sending of data from the buffer on the

opposite side has been completed.

(b) A BEMP interrupt is generated if data consisting of less than eight bytes is being written to the buffer on

one side and sending of data from the buffer on the opposite side has been completed.

(2) When the receiving direction (reading of the buffer memory) has been set

If the size of the data packet that was received exceeded the maximum packet size

At this point, if the other maximum packet size parameters were set to a value other than “0” ("MXPS≠0"), the

controller sets the PID bit of the pertinent pipe to “STALL”.

Figure 3.15 shows the timing at which BEMP interrupts are generated.

(1) Data transmission

(2) data reception

IN Token Packet

OUT Token Packet

ACK Handshake

Data Packet

STALL Handshake

Data Packet

USB bus

BEMP interrupt

Figure 3.15 Timing at which BEMP interrupts are generated

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