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M66592FP Datasheet(PDF) 62 Page - Renesas Technology Corp |
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M66592FP Datasheet(HTML) 62 Page - Renesas Technology Corp |
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62 / 127 page  M66592F P/W G Rev 1.00 2004.10.01 page 62 of 125 Table 3.8 shows the INT_N pin operations of the controller. If multiple interrupt causes have occurred, the method used for INT_N pin output can be set using the INTL bit of the INTENB1 register. The operation setting for the INT_N pin should be set to match the user system. Table 3.8 INT_N pin operations INT_N pin operation INTL setting When one interrupt cause occurred When multiple interrupt causes occurred Edge sensing (“INTL=0”) “L” level output until the cause has been eliminated When one cause is eliminated, the 32 clock time is negated (“H” pulse output) at 48 MHz. Level sensing (“INTL=1”) “L” level output until the cause has been eliminated “L” level is output until all of the causes have been eliminated. Interrupt cause 1 Interrupt cause 2 INT_N pin <Edge sensing> Cause 1 occurs Cause 2 occurs Cause 1 cleared Cause 2 cleared Negated interval Interrupt cause 1 Interrupt cause 2 INT_N pin <Level sensing> Cause 1 occurs Cause 2 occurs Cause 1 cleared Cause 2 cleared Figure 3.11 INT_N pin operation |
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